1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer interconnection structure with a thin film resistor and a method for manufacturing the same.
2. Related Arts
Some integrated circuits of semiconductor devices include thin film resistors formed on insulating layers as disclosed in, for example, JP-A-2-58259, JP-A-5-175428, and U.S. Pat. No. 5,382,916. Such thin film resistors are made of CrSi system material, NiCr system material or the like. Specifically, a thin film resistor made of CrSi system material (CrSi, CrSiN, or the like) has advantages such that the resistor can be easily formed in processes for manufacturing the semiconductor device, the resistor can have a resistance in a wide range including a low resistance and a high resistance, and the like. Further, a ratio of change in resistance of the CrSi system resistor can be controlled to be a positive or negative constant value or zero at a temperature within a range where the semiconductor device is generally used, by controlling a compositional ratio of the resistor or conditions of heat treatment performed on the resistor. Because of these reasons, the CrSi system resistor is noticed as a circuit element capable of being employed for various applications.
Conventional processes for forming such a thin film resistor made of CrSi that is applied to a semiconductor integrated circuit for a metal oxide semiconductor field effect transistor (MOSFET) as an example are shown in FIGS. 1 to 4. FIG. 1 shows a state where an FET region 2 is provided on a silicon substrate 1 by a transistor formation process. In this state, a source region 3 is formed in a surface portion of the FET region 2 to have a junction depth xj of, for example, approximately 0.45 .mu.m. Further, a local oxidation of silicon (LOCOS) layer 4, a gate oxide layer 5, a gate electrode 6 made of polysilicon, and a borophosphosilicate glass (BPSG) layer 7 are formed on the silicon substrate 1. Further, a contact hole 7a is formed in the BPSG layer 7 to expose the source region 3 by a wet etching treatment. Then, a CrSi layer 8a that is intended to be a thin film resistor 8 and a TiW layer 9a that is intended to be a barrier metal layer 9 are formed on an entire surface of the substrate 1.
Next, as shown in FIG. 2, the TiW layer 9a and the CrSi layer 8a are individually etched by a wet etching treatment and a dry etching treatment using photo resist 10 as a mask. As a result, the thin film resistor 8 and the barrier metal layer 9 are formed on the BPSG layer 7. During the dry etching treatment for the CrSi layer 8a, the surface portion of the silicon substrate 1 exposed from the contact hole 7a is etched. The etched depth of the silicon substrate 1 is approximately 10 .mu.m to 20 .mu.m.
Subsequently, as shown in FIG. 3, after the photo resist 10 is removed, a TiN layer 11 that is intended to be a barrier metal layer and a AlSiCu layer 12 that is intended to be a first Al layer (a first aluminum wiring) are formed and are patterned through a photo resist layer 13 serving as a mask by a dry etching treatment. This dry etching treatment utilizes a reactive ion etching (RIE) technique. During this etching treatment, the barrier metal (TiW layer) 9 prevents the thin film resistor 8 from being etched.
Next, as shown in FIG. 4, the TiW layer 9 except portions underlying the first Al layer 12 is removed by a wet etching treatment. Thereafter, the photo resist layer 13 is removed. Then, the processes for forming the thin film resistor 8 and the first Al layer are completed. The TiW layer 9 left between the first Al layer 12 and the thin film resistor 8 can prevent diffusion between the thin film resistor 8 and the first Al layer 12 to prevent deterioration of resistance characteristics of the thin film resistor 8. However, when the TiW layer 9 is etched, over-etching is usually performed to prevent the TiW layer 9 from remaining. This over-etching is likely to cause under-cut of the TiW layer 9 underlying the first Al layer 12 as indicated by arrows A in FIG. 4.